1. Field of the Invention
The invention relates generally to lithographic methods for forming patterned resist layers and patterned microelectronic layers within microelectronic products. More particularly, the invention relates to lithographic methods for accurately and efficiently forming patterned resist layers and patterned microelectronic layers within microelectronic products.
2. Description of the Related Art
As microelectronic device dimensions continue to decrease, difficulties in achieving critical dimension tolerances of microelectronic devices and patterned layers within microelectronic products generally continue to increase. Critical dimension tolerances may be influenced by various factors, not all of which are readily ascertained. Critical dimensions of microelectronic devices and patterned layers are defined employing lithographic methods, such as electron beam lithographic methods and photolithographic methods.
It is thus desirable to provide lithographic methods that in turn provide microelectronic devices and patterned layers with enhanced dimensional control. It is towards the foregoing object that the present invention is directed.
Various lithographic apparatus and methods having desirable properties have been disclosed in the microelectronic product fabrication art.
Included but not limiting among the apparatus and methods are those disclosed within: (1) Chen et al., in U.S. Pat. No. 6,210,843 (a differential electron beam dose method for forming a photomask with enhanced dimensional control); (2) Bode et al., in U.S. Pat. No. 6,368,883 (an apparatus and method for identifying and controlling effects of ambient conditions within photolithographic processes); and (3) Bode et al., in U.S. Pat. No. 6,535,774 (an apparatus and method that provide for enhanced overlay registration when forming patterned layers within microelectronic products).
The disclosure of each of the foregoing references is incorporated herein fully by reference.
Desirable are additional lithographic apparatus and methods for forming microelectronic devices and patterned layers with enhanced dimensional control within microelectronic products. The present invention is directed towards the foregoing object.